Creating the core of a directional antenna array transmission emulation, that is a digital implementation on an FPGA that showcases the capability to calibrate the transmission to a certain direction.
Project tag: xilinx
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Finds and detects a light source in a room by pointing at it. tries to track the light source on movement and keeps to point at it. -
Implementation of axi4 master according to axi4 protocol and integration with axi4 slave(from Xilinx) into Zedboard to verify them. -
Design an I2C Master controller capable to initiate write and read operations. Implementation of I2C Master as an IP block using Xillinx Vivado. -
Research project about Xilinx's Vitis-AI framework. Xilinx developed a unique and special ecosystem with dedicated software and hardware for accelerating deep neural networks and artificial intelligence applications. Our goal was to evaluate and validate this platform for future use. -
An FPGA project the aims to make the FPGA tests its own components and try to detect faults in the FPGA. For each components it's a different testing method in order to check whether the component is working as expected or not. -
This project includes design and implementation of a system that receives a video stream input and averages the colors of the pixels at the screen margins to get appropriate colors for LEDs in a LEDs chain that will be surrounding the screen. In other words, we will surround the screen with LEDs and give each led a color that is similar to the pixels located near this LED.Categories: IOT -
Embedded system implementation of a weather station with a display driver for the FMC-HMI display, atmospheric sensors, an RTC and a touchscreen GUI with a C graphical library. -
Hardware implementation of an artificial neural network on a Xilinx FPGA, to support advanced parallel calculations performed by dedicated software.Categories: Algorithms implementation -
This project offers an accelerator for neural network computations. Instead of performing the calculations in software using GPU, we implement a set of neurons that can perform the same calculations faster and concurrently in hardware on FPGA.Categories: Algorithms implementation -
The Inter-integrated Circuit (I2C) Protocol is a protocol intended to allow multiple "slave" digital integrated circuits ("chips") to communicate with one or more "master" chips. The goal of the project is to design and implement I2C master and slave on FPGA board for further uses. -
The ability to detect faces in live video is useful for many applications: cameras auto-focus, surveillance cameras, etc. The Viola-Jones algorithm was designed to deal with this problem using pre-trained filters to classify parts of the image as faces or none. To apply the algorithm on live video, our system is a HW implementation of the algorithm running on streaming video from camera and displaying live results on monitor. -
Video communication implementation between remote camera and screen using 2 ZedBoard cards. -
Fast communication channels have become a necessary infrastructure in any digital system. Industry defines various standards for transmitting data, one of the most important and common ones is the PCIe. The goal of the project is to design a Matlab GUI to allow the user to generate custom packets and Design a programmable data source for sending PCIe type package to a JBERT and analyze them there. -
In a CubeSat communication satellite which is scheduled to be launched in Q2 2020, a FPGA is used to interface some analog RF components to the PCIe bus of a processor. Up in space, the complete electronic of the satellite is subjected to a high degree of radiation. Radiation may lead to temporary or even permanent malfunction of the components e.g. the FPGA. As less than half the FPGA is... -
This goal of this project is a design of a compact sampling system as part of “Measurement on key” project. The system consist of a cheap ADC board and Zedboard card. The design consist of firmware and software code on the Zedboard, custem GUI and cables between Zedboard and ADC. -
This project implements an end-to-end system of Advanced Encryption Standard (AES) algorithm. The implementation includes encryption/decryption engine implemented on FPGA and full software stack for Linux for interface with the hardware. -
Voice Activated Technology - Identification and analysis of background noise. Differentiating between different sounds and giving proper indication. -
Car DVR (Digital Video Recorder), is a simple camera recording device. It is used to track driving habits, and provide evidence of car accidents. -
In this project, we emulate ultrasound data in the FPGA and send it through a loopback to the FPGA, we preprocess the data by interpolation filtering, delaying and packing to produce a low focused single beam of 128 bit. The beam data is then transferred to a host system for further processing via DMA on a PCI-express bus. -
A touch and display controller supporting FMC-HMI card. The HDL code targets Zedboard, which is connected to the FMC-HMI through the FMC and XADC interfaces. Recognize when and where the display is touched, draws crossed lines in exact location on LCD. -
Weather Station remotely managed by Amazon AWS IOT services. -
The IoT ("Internet of Things") is a big trend in the industry nowadays, and one of the most commonly used products in IoT networks is a remote-controlled web camera. The purpose of this project was to build such a system, using two Zedboards (SoPC), a joystick, a screen, a motor controller and a stepper motor. -
Implementing FPGA Bridge between High Speed Channel (Local Network) & Ethernet (External Network). The conception is to create a mutual environment (accelerator) to provide the ability to communicate between the two networks with high rates, utilizing the high capabilties of the Xilinx Virtex 6 FPGA. -
PowerBench - A versatile power supply unit with multiple outputs for laboratory use and testing of various electronic devices. This project concentrates on FPGA design and embedded software. -
The project is part of the Sub-Nyquist sampling and reconstruction card. Our goal was to implement DSP unit on FlexRio FPGA card under NI LabView environment, it includes integration to the full system (NI Chassis with 3 FlexRio FPGA cards). -
The project goals is to design and implement on FPGA device FFT that capable to deal with high rate data processing (rates up to 10MSamp/sec*). *- 5Ms/sec for each of I and Q components . -
Implementation of a digital receiver according to the theory of the OFDM on a FPGA from VIRTEX 5 family. -
Design and implement of the Heterogeneous Network-on-Chip (NoC) router system. -
Implementation of LZRW3 data compression algorithm. -
The goal of this project was to implement an interactive embedded system, based on MicroBlaze processor and Linux OS, interacting with user through a PS2 keyboard and using an LCD screen as an output. -
Implementation of configurable General Purpose FIFO and IP core generator for the GP FIFO. -
Implementation of Out-of-Order execution engine on the base of OpenRISC architecture. -
Neural Network is a Machine Learning System designed for supervised learning using examples. Such network can be used for handwritten digit recognition, and when used in software is in-efficient in both time and resources. This project is the third part of a 3-parts project. Our goal is to implement an efficient hardware solution to the handwritten digit recognition problem. Implementing dedicated HW to this task is part of a new... -
Implementation of high-speed and real-time 2-D Discrete Wavelet Transform, based on new and fast convolution approach, and usage of efficient memory area (in-place). -
This project aim was to create an infrastructure who enable the end user to create and use hardware accelerators library using INtime for Windows RTOS and NetFPGA-SUME. Hardware accelerators are created with Xilinx Partial Reconfiguration technology that gives us the ability the ability to swap accelerators at real-time without affecting other operational part of the system.Categories: Embedded Systems -
Creating a core that encrypts/decrypts data quickly and efficiently using FPGA. -
In this project we planned a sinus generator system that is configured online by the user. -
Using Xilinx partial reconfiguration technology, we implemented an ability to change the hardware system dynamically due to the application request. The hardware change is done at runtime by application & OS and the custom hardware can be supplied by the application user. -
Independent system connected to the Internet that can transfer data and control from and to a PC and store large amount of data transferred from a PC on the DDR. -
System for sub-nyquist sampling in SMPL lab at the EE faculty at Technion. It will provide a flow of pre-defined signals in high frequency (6.1 GHz) to the client system which would use the data in order to reconstruct sampled signals in sub-Nyquist rate. -
The project goal is designing high speed decompression core and assemble its periphery units using VHDL language so it could be properly implemented on an FPGA. -
Building an infrastructure for hardware accelerators based on FPGAs for algorithms implemented in MATLAB. Consists of 3 main parts: - C code that is invoked from a MATLAB script (MEX file). - PCIe driver that is used to transfer data to the hardware. - Basic hardware design that connect the PCIe and the DDR3 memory DIMMs on the VC709 board. -
The ZED-board has an RGB output port. This port must be driven from logic in the reconfigurable logic portion of the FPGA. Aims is, to create a frame-buffer in memory, to be filled with data by a program running on an ARM, read its content via AIX DMA (Direct Memory Access) and send it to the logic to be created in VHDL for display on a RGB display. -
Implementation of the JPEG decompression algorithm using the Xilinx VIVADO HLS -
The project's goal is to implement an SOC architecture that could compute a wide variety of Deep Learning algorithms using Convolutional Neural Networks in a fast, dynamic and configurable way. -
In this project we developed and implemented testing environment for Detection of low intensity and short duration light pulses for SPAD chip (Ver. 2). -
Hardware DLL - Real Time Partial Reconfiguration Management of FPGA by OS.