Implementation of configurable General Purpose FIFO and IP core generator for the GP FIFO.
In this project we implemented General Purpose FIFO, based on DDR3 memory. The FIFO is configurable and has simple interface. GP FIFO can be a lot bigger then any default FIFO on a board. Its depth gives us opportunity to store big chunks of data very fast and then process it at slower rate.
To make process of integration and communication simple for user, we built IP Core generator for GP FIFO and example design which can establish connection to Host computer through Ethernet.