Implementation of a digital receiver according to the theory of the OFDM on a FPGA from VIRTEX 5 family.
Projects
Description.
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Learning and implementing testing methodologies for a multi-core chip made by Plurality. tests include : memory, register file, ALU unit, program counter. algorithms: March13N, Galpat, GalRow. -
Jitter is a significant phenomena at high speed communication lines which strongly affects signal integrity. Therefore it is important to be able to artificially create different types of jitter in order to explore its implications and use it for educational purposes. -
The goal of this project is to develop a smart traffic lights system that could sense real time changes in volume and speed of traffic. Using BT and WiFi signals, the system extracts statistical information on the road. According to that, a policy of traffic light would be determined, in order to receive a wardrop (equilibrium). -
Electricals lines on systems running in harsh environments are prone to failure. Electrical disconnectivity is very common and could have severe consequences. The project offer on-line, easy, cheap and very accurate way called Passive TDR to discover electricals disconnections and locate where they are. -
The project 'IOT for a Car' belongs to the IOT area. This project deals with developing an alert System, located in a car, which sends reports to the car owner in cases of emergency. -
Construction of the most effective neutrino detector to be installed at the south pole. -
Scan Insertion is a powerful product testing technique commonly used nowadays. Unfortunately, when security is a concern, scan insertion may pose a major problem. In our project, we exploited this vulnerability for reverse engineering purposes. -
Developing an electronic door eyepiece as part of the IOT revolution. Delivering a real time photo of your home, reachable from any device. Motivated by comfort and home security low cost components now enable us to integrate technology in quotidian life. -
The aim of this project is to explore system-induced distortion mechanisms and analyze their effects on binary and CW signals integrity. Modern high-speed digital systems require data rates in excess of 1GHz These rates, and the resulting system bandwidths, pose severe design challenges aimed to minimize the system-induced distortions that affect negatively the binary signal integrity and the ability of the decoding sytem to recover the digital data correctly. The... -
In this project we implemented a waveform generator on a FPGA that gets the commands from a connection to a PC. It is then transferred to a simple DAC and an analog waveform is created. The user sends his choice to the system – the wave shape and all the other parameters. -
The FPGA Based Calculator Core Project main goal is to implement a calculator for simple algebraic calculations, using hardware. -
Scope is utilized as a primary testing instrument for time domain signals. Its multi channel and coherent sampling capabilities makes it useful for a variety of applications in different and complex engineering disciplines. Automation of the scope is essential for an efficient utilization of the platform. MATLAB, in conjunction with its Instrumentation Control Toolbox , is an ideal SW platform to both control the instrument parameters and acquisition properties, as... -
For decades, radar sampling was constrained to the Nyquist theorem. Recently, new research has provided techniques to sample short-time pulses in sub-Nyquist rates, and to reconstruct them in efficient robust ways. Our project studies the existing techniques and further improves them to achieve both noise robustness and estimation accuracy. -
Project Wisdom Stone GUI implementation The goal of the project to implement GUI in c++ , for specific board that allows to control over all the function of the board. connection way is usb or wireless. -
A portable, low-power system that will check the eyelid movements and analyzed the results. -
CHUM - Cross Hole Ultrasonic Monitor is a device designed by Piltest in order to monitor deep concrete foundations, using ultrasonic waves. The project requires developing a daughter-board based on FPGA and ADC, that samples data at higher rates than before, and connects to a CHUM mother-board. -
Smart Application Specific FPGA based SAT Solver -
The Symbol Generator includes a software symbol generator (using Matlab) with a HW extractor (FPGA) using VHDL. Using a set of known symbols (such as letters, digits, icons, etc), all having in common the same dimensions, and are generated on the screen. The goal is to save time, resources and bandwidth. Therefore, the SW transfers to the HW only the change of the wanted frame from the current one, using... -
In this project we implemented a full communication system (Transmitter & Receiver). The system supports two modulation types: QPSK and 8-PSK. The work environment of the project was NI-Labview, and the system was designed to work at high speed rates on FPGA. -
Infrastructure design implementation of particle filter using bluespec HDL -
Joint project with the physics faculty, the objective of which is to build a system that interfaces with a PC on the one end and controls an adaptive mirror that is connected to it on the other end. An adaptive Mirror – contains 59 capacitors to control the convexity in order to correct distortions of light. -
The project implements an image processing algorithms with VHDL. The system burn on FPGA board, and supports: Full panoramic rotation: -360 to 360 degrees Zoom function- x1 to x16 Crop-Image function Minimum image distortion. Inputs - angle, zoom factor, crop coordinates, 512x512 BMP 8bit greyscale image. Output - processed 600x800 BMP 8bit greyscale image. Protocols - UART-software to hardware, WISHBONE-hardware to hardware. -
Automatically generates registers according to a required specification using a smart interface. -
Build a super computer system which delivers a large bandwidth to a single 10Gps Network interface card (NIC). -
Cryptography System using AES (Advanced Encryption Standard) Algorithm, implemented with VHDL, on FPGA Cyclon II component on DE2 Altera Board. -
Design and implementation of Portable ECG device based on FPGA. -
Design and implement of the Heterogeneous Network-on-Chip (NoC) router system. -
Implementation of LZRW3 data compression algorithm. -
Development of device that facilitates the monitoring of the upper eyelids motion, acquires the eyelid vertical movement and enables analysis and graphic presentation of the results. It should allow the patient to move freely in his/her natural environment. The primary purpose is to monitor eyelid movements and to compute the relevant eyelid movement parameters -
Ultrasound imaging requires large amount of data to be collected and processed. New studies try to reduce the amount of data by using Sub-Nyquist techniques. The project continues this work and suggest a new digital processing method which greatly improves image quality and computation complexity. -
Hardware which connects to a vehicle computer along with peripherals (barometer and accelerometer) intended to be able to find the road grade. -
The goal of this project is to build a simulation environment for the system and to compare different compressed sensing strategies within this setting. -
The goal of this project was to implement an interactive embedded system, based on MicroBlaze processor and Linux OS, interacting with user through a PS2 keyboard and using an LCD screen as an output. -
An Android application which monitors CAN communication and maps between vehicle devices and their addresses. -
Optical flow is an image processing algorithm that produces a 2D vector field of the speed of every pixel in a movie. In this project we implemented a basic optical flow algorithm in Simulink as a real time hardware system for future loading onto a FPGA. -
The purpose of this project is to build a complete DAQ system from one chip. One of the most important benefits from this are it cost. -
Implementation of configurable General Purpose FIFO and IP core generator for the GP FIFO. -
The project implemented Internal Logic Analyzer, a checking device which assist debugging the FPGA card. The device is independent in the manufacturer of the card. The project was written in VHDL code. Both entering data into the system and extracting it are according to UART protocol. In the system there is a possibility for the user to define the depth and the width of the recorded data as he wishes,... -
Develop a device for monitoring eyelid motion, acquiring the eyelid movements and enabling analysis of the results. -
Implementation of Out-of-Order execution engine on the base of OpenRISC architecture. -
In our project, we were asked to design and implement an architecture for verification of Encryption\Decryption systems, to be used on Disk-On-Keys. -
Kuala project's goal was to build an electronic system which would ensure the possibility of relaying the information gathered by the stones with as little physical presence as possible. -
The project main goal is to create a "stone" that would be buried under the road, and sensing the vibration the creates by the traffic, and by this, getting informed for if the road is about to be ruined, and be able fixing it before it actually happens. -
Bluespec SystemVerilog (BSV) is very high-level, fully synthesizable hardware description language (HDL). In this project we implement RISC multi core processor using Bluespec while relaying on 2 stages pipeline SMIPS single core processor. The multi core design shall be evaluated and analyzed compared to single core design in order to examine performance improvement. -
Neural Network is a Machine Learning System designed for supervised learning using examples. Such network can be used for handwritten digit recognition, and when used in software is in-efficient in both time and resources. This project is the third part of a 3-parts project. Our goal is to implement an efficient hardware solution to the handwritten digit recognition problem. Implementing dedicated HW to this task is part of a new... -
Implementation of high-speed and real-time 2-D Discrete Wavelet Transform, based on new and fast convolution approach, and usage of efficient memory area (in-place). -
Compare the results of physical test using J-Bert and trace PCB Board to simulation the same tests using Cadence Sigrity simulation software. -
Implementation of data cryptography embedded system using AES algorithm on Zync SoC. Finding the suitable architecture for portable system. -
This project aim was to create an infrastructure who enable the end user to create and use hardware accelerators library using INtime for Windows RTOS and NetFPGA-SUME. Hardware accelerators are created with Xilinx Partial Reconfiguration technology that gives us the ability the ability to swap accelerators at real-time without affecting other operational part of the system.Categories: Embedded Systems -
The goal of this project was to design and implement a request-response predictor for NoC-based CMP, in order to maintain an "open channel" in the pipeline, and to reduce latencies in the NOC system. -
This project deals with the problem of detecting a vehicle’s speed on highways. The purpose of the project is to create a device that will be able to identify vehicles and calculate their speeds automatically. -
Finding optimal Mixing sequences for effective signal reconstruction. Finding the characteristics of those sequences -
Expander implementation using filter banks -
Implementation of the Cyclostationary feature detection Algorithm. -
Creating a core that encrypts/decrypts data quickly and efficiently using FPGA. -
The goal of the project is to build a multicore system based on the OpenRISC architecture, and implement it on Xilinx XUPV5 (aka ML509) board. -
The project goal is to Create a FIR filter that can process pulses from photon counting detectors and perform Peak Detection using NI Labview FPGA. Trapezoidal Filter is a type of Shaper(time domain filters for nuclear spectroscopy), it used in order to get optimal noise performance from signal. Trapezoidal Shaper immune to “ballistic deficit”, that causes energy distortion in the spectrum. -
The project consists of two main goals: 1)Low SNR Performance - By improving Doppler frequency and using knowledge from different speed bins we are able to better differentiate between targets and improve low SNR performance 2) Model Order Estimation - We compare 3 different methods of establishing a scenarios noise floor using false detection and hit/miss benchmarks -
Design and implement a web based system that will process and display various data that is collected from a vehicle computer. -
Infrastructure design & implementation of MIPS processors for students lab - based on Bluespec HDL -
Building a Flash Memory controller, which support standard Open NAND Flash Interface on one side and allow accessing the data in memory from the other side. -
In this project we tested using the earth as a communication channel between people hundreds of feet deep in the ground and surface. The communication must be wireless. -
Cryptography System using RSA Algorithm, implemented with VHDL, on FPGA. -
Designing a controller for flash memory that implements reading, writing and erasing. -
Implementing Pipelined MIPS processor using Bluespec System Verilog, and run it on FPGA. -
In this project we planned a sinus generator system that is configured online by the user. -
Using Xilinx partial reconfiguration technology, we implemented an ability to change the hardware system dynamically due to the application request. The hardware change is done at runtime by application & OS and the custom hardware can be supplied by the application user. -
Independent system connected to the Internet that can transfer data and control from and to a PC and store large amount of data transferred from a PC on the DDR. -
The goal of this project is to design and implement an efficient architecture for reconstruction of a compressed image by DWT transform. -
The project focused on the signal analysis section of the system: Studying the signal at each point throughout the system, and defining the expected signal for various blink patterns, on each output of the system’s 8 sensors. -
A Picture In Picture is an additional video\picture data placed in a main video data frame, by using FPGA. -
The project goal was to develop a power delivery system based on Magnetic resonance. In addition to develop a compensation loop to reach peak power delivery at resonance frequency. -
In this project we have designed a board that would allow operation of new system aimed for Fuel Saving System for heavy trucks fleets. The system provides 3D-mapping support, and fuel performance mapping support. -
System for sub-nyquist sampling in SMPL lab at the EE faculty at Technion. It will provide a flow of pre-defined signals in high frequency (6.1 GHz) to the client system which would use the data in order to reconstruct sampled signals in sub-Nyquist rate. -
The project goal is designing high speed decompression core and assemble its periphery units using VHDL language so it could be properly implemented on an FPGA. -
The purpose of the Wisdom Stone project is to enable road monitoring with minimal operational effort. -
An Engine Control Unit based on an Intel Galileo SoC. The ECU is a real time system that reads the engine sensors and determines the ideal fuel amounts and ignition times. -
Implementing a location tracking system based on ultra sound waves, for indoor use -
Implementation of mini digital scope. User can determine the pre and post trigger, trigger level, how many sequential times user want to find the trigger. Using the wishbone protocol for communication between different system blocks. -
Building an infrastructure for hardware accelerators based on FPGAs for algorithms implemented in MATLAB. Consists of 3 main parts: - C code that is invoked from a MATLAB script (MEX file). - PCIe driver that is used to transfer data to the hardware. - Basic hardware design that connect the PCIe and the DDR3 memory DIMMs on the VC709 board. -
The aim of this project is to develop a receiver for capsule magnetic signals allowing future integration in the embedded Capsule Positioning System. -
Developing an efficient algorithm specially tailored for implementation on FPGA for efficient matrix multiplication. -
Designing an autonomous remote control car using the Intel Galileo platform. -
Design and simulate a low-cost sampler for high frequency short pulses, with low power consumption. -
Planning and construction of a smart home system which will be based on the Arduino micro controller. The system will be connected to the Internet, and will be able to take orders over it. -
In this project we designed and programmed an infrastructure for an interactive home based on voice recognition using Galileo and Raspberry Pi. -
The project main goal is to build a smart home infrastructure. -
Designing fast clock source with deterministic jitter for high speed phenomena experiment. -
The goal of this project is to enhance a design of a basic CFMT architecture and test the performance by running SPEC CPU 2006 benchmarks. -
Design universal infrastructure for encryption/decryption system using FPGA. -
The project goal is a detection of fast and low illumination light pulses in maximum light condition. This is done by using the SPAD (Single Photon Avalanche Diode). -
Perform complex video processing by hardware, software and both with embedded system. The embedded system is based on the ZYNQ component of Xillinx and FMC module. -
CORDIC is an acronym for COrdinate Rotation DIgital Computer. It is a class of shift-add algorithms for rotating vectors in a plane. In a nutshell, the CORDIC rotator performs a rotation using a series of specific incremental rotation angles selected so that each is performed by a shift and add operation. The project goal is to implement the CORDIC algorithm in HDL language, choose optimal architecture and test it on FPGA card -
The ZED-board has an RGB output port. This port must be driven from logic in the reconfigurable logic portion of the FPGA. Aims is, to create a frame-buffer in memory, to be filled with data by a program running on an ARM, read its content via AIX DMA (Direct Memory Access) and send it to the logic to be created in VHDL for display on a RGB display. -
This project implements a controller for a bio potential simulator, using NI labview FPGA. -
Implementation of the JPEG decompression algorithm using the Xilinx VIVADO HLS -
The Eyelid motion monitor project's vision is to create a device that will allow doctors to diagnose medication effects and neurological diseases by characterizing the eyelid movement of a patient. -
This project deals with planning a pulse generator using NetFPGA SUME. -
Design and implement a Graphical User Interfaced control program for Mellanox Technologies products SerDes block. The program configures the SerDes operation mode according to user input, and displays the RX BER Eye Diagram, a tool for measuring transmission quality.