Risc-V experiment project with a main goal of developing a lab experiment for the HSDS laboratory. The experiment’s purpose is to teach students and show them in detail how exactly the Risc-V processor works.
Project tag: risc V
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This project explores a simple design and implementation of a Vector Processing Unit attached to a RISC-V Multi-Cycle microarchitecture core. We implemented the design on an FPGA, executed code, measured and compared performance and power on the integer-processor versus our vector-processor. The comparative evaluation showed that in the cost of quadruple the hardware, we got significant differences in favor of vector-processor, both in energy and execution time.Categories: Algorithms implementation -
STT-MRAM is a new emerging memory technology. Based on a JEDEC-DDR3 compatible MRAM device, this project studied an evaluated the performance and possible usages of the technology in modern day systems. -
There are many RISC-V designs and implamantations. The project review and supply full development environment for two of them.