There are many RISC-V designs and implamantations.
The project review and supply full development environment for two of them.
RISC-V is the only processor that has a completely open source instruction set (ISA).
The ISA was developed by UC Berkeley, and allows a simple, clean, stable and modular ISA.
The project reviews the varied implementations in order to ease the decision, which platform to use, according to the future project’s needs.
The project focus on two implementations:
Rocket:
Developed by UC Berkeley, continued by Si-Five (commercial company).
Rocket Chip is an open-source System-on-Chip out-of-order design generator.
It uses Chisel- hardware construction language, to construct a library of generators for every part of SoC.
Pulpissimo:
Developed by ETH Zurich and University of Bologna.
Pulpissimo is a single-core platform and supports all 32-bit RISC-V cores in PULP “family”- RI5CY, Zero-RI5CY and Micro-RI5CY.
It uses SystemVerilog and allows diverse simulation options.
Both has full development environment installed and short manuals, in order to start work with them instantly.
