STT-MRAM is a new emerging memory technology. Based on a JEDEC-DDR3 compatible MRAM device, this project studied an evaluated the performance and possible usages of the technology in modern day systems.
The new MRAM technology is non-volatile, offers high cell density and does not require refresh operations to sustain data integrity.
Despite of its advantages, it suffers from long timing constraints, making it slow and inefficient in cases of low-locality access patterns.
In this project, two main design products were created. Both designs can function in either SDRAM/MRAM DDR3 mode:
• A memory simulation model
• A memory controller
The controller was designed based on the Xilinx MIG PHY-Only infrastructure to allow synthesis for a Xilinx ZC706 board and the simulation model was made to accompany it as a proof that the controller is viable.
Using the controller design, a performance comparison and analysis has been performed to assess the technology’s advantages and vulnerabilities.
Though synthesis of the controller for the board ultimately failed, as the design was un-synthesizable, simulations were fruitful, and provided important insight. It is assumed that the synthesis issues can be resolved to provide physical proof-of-concept for the controller functionality.
