pcie Archives - Diglab

PCIe GEN 3.0 network analyzer

Fast communication channels have become a necessary infrastructure in any digital system. Industry defines various standards for transmitting data, one of the most important and common ones is the PCIe. The goal of the project is to design designing and building a serial data receiver using the FPGA board, which receives data from the Jbert and forward it to transmitter which transmits it back to the JBERT and analyze the...

Tags: high frequency | jbert | pcie

PCIe GEN 3.0 PBERT analyzer

Fast communication channels have become a necessary infrastructure in any digital system. Industry defines various standards for transmitting data, one of the most important and common ones is the PCIe. The goal of the project is to design a Matlab GUI to allow the user to generate custom packets and Design a programmable data source for sending PCIe type package to a JBERT and analyze them there.

Tags: netfpga | PBERT | pcie | xilinx

Data Acquisition and Preprocessing for Medical Ultrasound

In this project, we emulate ultrasound data in the FPGA and send it through a loopback to the FPGA, we preprocess the data by interpolation filtering, delaying and packing to produce a low focused single beam of 128 bit. The beam data is then transferred to a host system for further processing via DMA on a PCI-express bus.

Tags: lvds | netfpga | pcie | ultrasound | xilinx

16Ghz Clock Source for PCIe Gen4

This project presents the design, analysis and testing of a PCIe 4.0 PBERT clock source module. The design includes two PLL synthesizer modules and a controller. The first module outputs a clean 200MHz clock for an FPGA, while the second outputs a 16GHz data-rate clock. The 16GHz clock can be output very clean (less than 10mUI) or modulated to add random or deterministic jitter as desired.

Tags: bert | Clock source | jbert | PBERT | pcie

Processor architecture exp.

Infrastructure design & implementation of MIPS processors for students lab - based on Bluespec HDL

Tags: Bluespec | mips | pcie | scemi | xup5

Hardware Accelerator for Matlab

Building an infrastructure for hardware accelerators based on FPGAs for algorithms implemented in MATLAB. Consists of 3 main parts: - C code that is invoked from a MATLAB script (MEX file). - PCIe driver that is used to transfer data to the hardware. - Basic hardware design that connect the PCIe and the DDR3 memory DIMMs on the VC709 board.