Project tag: PBERT

  • PCIe GEN 3.0 PBERT analyzer

    Fast communication channels have become a necessary infrastructure in any digital system. Industry defines various standards for transmitting data, one of the most important and common ones is the PCIe. The goal of the project is to design a Matlab GUI to allow the user to generate custom packets and Design a programmable data source for sending PCIe type package to a JBERT and analyze them there.
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  • 16Ghz Clock Source for PCIe Gen4

    This project presents the design, analysis and testing of a PCIe 4.0 PBERT clock source module. The design includes two PLL synthesizer modules and a controller. The first module outputs a clean 200MHz clock for an FPGA, while the second outputs a 16GHz data-rate clock. The 16GHz clock can be output very clean (less than 10mUI) or modulated to add random or deterministic jitter as desired.
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