The project goals is to design and implement on FPGA device FFT that capable to deal with high rate data processing (rates up to 10MSamp/sec*). *- 5Ms/sec for each of I and Q components .
Project tag: ml605
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Implementation of configurable General Purpose FIFO and IP core generator for the GP FIFO. -
Neural Network is a Machine Learning System designed for supervised learning using examples. Such network can be used for handwritten digit recognition, and when used in software is in-efficient in both time and resources. This project is the third part of a 3-parts project. Our goal is to implement an efficient hardware solution to the handwritten digit recognition problem. Implementing dedicated HW to this task is part of a new...