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Project tag: de2
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"Real Time Tracking Algorithm On Low Cost Fpga" consists of two parts: Part A: A system that streams video to DE2 board and displays them on a CRT/LCD screen Part B: Implementation of a video tracking algorithm on FPGA both in hardware and software. -
The project is 2-semestrial and includes working with Altera DE-2 and DE-3 educational boards, USB analyzer and USB webcam. In the first part of the project we built and configured the system which runs on Altera DE2 board and operates USB interface with generic webcam. We implemented USB host interface which enables to detect, configure the video cam and get isochronous video stream. The video stream is then decoded and... -
Implementing simple calculator over Ethernet using NIOS II on Altera DE2 board. Using PC Ethernet interface for input and result output. -
The project is an implementation of a controller to the "High Speed Exeperiment" done in the HS DSL. The project was implemented on the DE2 education board and contains GUI implemented with Matlab. -
The FPGA setting using FLASH Project consists of 3 main parts: a software component (host), hardware on FPGA, and FLASH memory. The software component is a MATLAB based GUI for writing, reading, and erasing data on the FLASH memory. The hardware on the FPGA is the link between the software and the FLASH memory. It reads data stored in FLASH once power is turned on and configures on board clients.... -
In computer graphics, ray tracing is a technique for generating an image by tracing the path of light through pixels in an image plane and simulating the effects of its encounters with virtual objects. The technique is capable of producing a very high degree of visual realism, usually higher than typical scan-line rendering methods, but at a greater computational cost. This makes ray tracing best suited for applications where the... -
In High - speed communication, data is usually transferred in a serial way, being de-serialized at the receiver. When no-handshake is used, synchronization and alignment problems may arise. The project goal is to solve this issue by adding a protocol layer over the physical layer, which allows data packets transfer between a transmitter and a receiver, while assuring it to be synchronized and aligned properly, with low error probability. The... -
In our project, we will design the implementation for the CEDAR algorithm over Hardware Description Language, and using functional simulations, we will demonstrate how the CEDAR algorithm can achieve low relative errors while keeping a small number of bits per counter. -
Today, array sorting is a highly required task. Generating a photo histograms on cameras, folder and file trees on computers, displaying a contact list on a cell phone - all use sorting. Therefore, a quick and efficient sorter will be very useful. This project implements a sorting mechanism that receives an input stream of integer arrays and outputs sorting results in real time, and with zero latency. To do so,... -
WRR algorithm (Weighted Round Robin) arbitrates between clients, requesting usage of the same resource. Arbitration is based on a simple round robin algorithm (clients are granted in a cyclic order), but the grant period for each client is related to its current weight. The project goal is to implement a WRR Arbiter on an FPGA with RT configurable weights. The WRR ARBITER design is implemented on a Cyclone II FPGA... -
The project compresses, using Run-length algorithm (sequences in which the same data value occurs in many consecutive data elements is stored as a single data value and count, rather than as the original run), image using MATLAB and transmits it, as a wrapped message, through UART protocol, to the DE2 board. The FPGA encodes the wrapped message, validate CRC and correct message length and stores the data into SDRAM. The... -
The FPGA Based Calculator Core Project main goal is to implement a calculator for simple algebraic calculations, using hardware. -
Smart Application Specific FPGA based SAT Solver -
The Symbol Generator includes a software symbol generator (using Matlab) with a HW extractor (FPGA) using VHDL. Using a set of known symbols (such as letters, digits, icons, etc), all having in common the same dimensions, and are generated on the screen. The goal is to save time, resources and bandwidth. Therefore, the SW transfers to the HW only the change of the wanted frame from the current one, using... -
The project implements an image processing algorithms with VHDL. The system burn on FPGA board, and supports: Full panoramic rotation: -360 to 360 degrees Zoom function- x1 to x16 Crop-Image function Minimum image distortion. Inputs - angle, zoom factor, crop coordinates, 512x512 BMP 8bit greyscale image. Output - processed 600x800 BMP 8bit greyscale image. Protocols - UART-software to hardware, WISHBONE-hardware to hardware. -
Cryptography System using AES (Advanced Encryption Standard) Algorithm, implemented with VHDL, on FPGA Cyclon II component on DE2 Altera Board. -
Design and implementation of Portable ECG device based on FPGA. -
In our project, we were asked to design and implement an architecture for verification of Encryption\Decryption systems, to be used on Disk-On-Keys. -
Designing a controller for flash memory that implements reading, writing and erasing. -
Design universal infrastructure for encryption/decryption system using FPGA. -
CORDIC is an acronym for COrdinate Rotation DIgital Computer. It is a class of shift-add algorithms for rotating vectors in a plane. In a nutshell, the CORDIC rotator performs a rotation using a series of specific incremental rotation angles selected so that each is performed by a shift and add operation. The project goal is to implement the CORDIC algorithm in HDL language, choose optimal architecture and test it on FPGA card -
This project uses symbol generator infrastructure. The main goal is to enable navigation between symbols that can be generated in advance.