Algorithms implementation Archives

Vector Accelerator for RISC-V architecture

This project explores a simple design and implementation of a Vector Processing Unit attached to a RISC-V Multi-Cycle microarchitecture core. We implemented the design on an FPGA, executed code, measured and compared performance and power on the integer-processor versus our vector-processor. The comparative evaluation showed that in the cost of quadruple the hardware, we got significant differences in favor of vector-processor, both in energy and execution time.

Categories: Algorithms implementation

Tags: netfpga | risc V | Vector accelerator

Neuron Cell Implementation on FPGA

Hardware implementation of an artificial neural network on a Xilinx FPGA, to support advanced parallel calculations performed by dedicated software.

Categories: Algorithms implementation

Tags: fpga | Neural Network | Neuron | xilinx | zedboard

Neural Network Implementation in Hardware (fixed point)

This project offers an accelerator for neural network computations. Instead of performing the calculations in software using GPU, we implement a set of neurons that can perform the same calculations faster and concurrently in hardware on FPGA.

Categories: Algorithms implementation

Tags: fpga | Neural Network | xilinx | zedboard

Multi-threaded Systolic Array on FPGA

Systolic arrays are a latency-efficient way to compute matrix calculations - specifically matrix multiplication. Sparse matrices cause under utilization of the array because of the zeros. In an attempt to boost utilization, these empty cycles can be used to compute results of a different calculation thread thus also boosting overall performance. This project goal implementing a regular systolic array as well as a multi threaded systolic array in FPGA to...

Categories: Algorithms implementation

Tags: Systolic Array