ASIC Tester Developing a generic testnig system which supports up to 96 i/o 100Mhz clock rate and -10v - 10v supply Tags: altera | asic | Gidel | proce | procwizard | quartus
Mini digital signal scope Implementation of mini digital scope. User can determine the pre and post trigger, trigger level, how many sequential times user want to find the trigger. Using the wishbone protocol for communication between different system blocks. Tags: altera | quartus | scope | vhdl | wishbone
Menu Navigation This project uses symbol generator infrastructure. The main goal is to enable navigation between symbols that can be generated in advance. Tags: altera | de2 | menu | quartus