The project implements an image processing algorithms with VHDL. The system burn on FPGA board, and supports: Full panoramic rotation: -360 to 360 degrees Zoom function- x1 to x16 Crop-Image function Minimum image distortion. Inputs - angle, zoom factor, crop coordinates, 512x512 BMP 8bit greyscale image. Output - processed 600x800 BMP 8bit greyscale image. Protocols - UART-software to hardware, WISHBONE-hardware to hardware.
