![](https://diglab.technion.ac.il/wp-content/uploads/sites/5/2016/09/small_pic-900x539.png)
This project aim was to create an infrastructure who enable the end user to create and use hardware accelerators library using INtime for Windows RTOS and NetFPGA-SUME. Hardware accelerators are created with Xilinx Partial Reconfiguration technology that gives us the ability the ability to swap accelerators at real-time without affecting other operational part of the system.
Categories:
Embedded Systems