An implementation of an infrastructure of low power, high range and scalable network of sensors used to efficiently collect information in a secured manner
Hardware acceleration is necessary to improve network performance. The goal of the project is to implement compression of packets data in real time on a FPGA integrated inside a network card.
In our project, we will design the implementation for the CEDAR algorithm over Hardware Description Language, and using functional simulations, we will demonstrate how the CEDAR algorithm can achieve low relative errors while keeping a small number of bits per counter.
Neural Network is a Machine Learning System designed for supervised learning using examples. Such network can be used for handwritten digit recognition, and when used in software is in-efficient in both time and resources. This project is the third part of a 3-parts project. Our goal is to implement an efficient hardware solution to the handwritten digit recognition problem. Implementing dedicated HW to this task is part of a new...
The project's goal is to implement an SOC architecture that could compute a wide variety of Deep Learning algorithms using Convolutional Neural Networks in a fast, dynamic and configurable way.