Out of order Open Risc Implementation of Out-of-Order execution engine on the base of OpenRISC architecture. Tags: cpu | open cores | open risc | xilinx | xup5
Multi core system using openRisc The goal of the project is to build a multicore system based on the OpenRISC architecture, and implement it on Xilinx XUPV5 (aka ML509) board. Tags: cpu | multi core | openrisk | risk | xup5