Infrastructure design implementation of particle filter using bluespec HDL
Project tag: Bluespec
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Bluespec SystemVerilog (BSV) is very high-level, fully synthesizable hardware description language (HDL). In this project we implement RISC multi core processor using Bluespec while relaying on 2 stages pipeline SMIPS single core processor. The multi core design shall be evaluated and analyzed compared to single core design in order to examine performance improvement. -
Infrastructure design & implementation of MIPS processors for students lab - based on Bluespec HDL -
Implementing Pipelined MIPS processor using Bluespec System Verilog, and run it on FPGA.