Implementation of axi4 master according to axi4 protocol and integration with axi4 slave(from Xilinx) into Zedboard to verify them.
Project tag: axi
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The ZED-board has an RGB output port. This port must be driven from logic in the reconfigurable logic portion of the FPGA. Aims is, to create a frame-buffer in memory, to be filled with data by a program running on an ARM, read its content via AIX DMA (Direct Memory Access) and send it to the logic to be created in VHDL for display on a RGB display.