Nowadays, many VLSI (Very Large Scale Integration) components are manufactured in the industry. After manufacturing these components, there is need for component validation before composition in a larger system, or delivering the products to the client. In spring 2009, VLSI Lab offered a Tester for VLSI components project to HSDSL. In our project, the main idea was to create a custom HW and SW solution that will allow examining different...
Project tag: asic
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Developing a generic testnig system which supports up to 96 i/o 100Mhz clock rate and -10v - 10v supply
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Developing a generic testnig system which supports up to 96 i/o pins, 100Mhz clock rate, loop mode (loop over the data according to loop commands received from the user ), adding embedded logic analyzer to view and anlyze the signals from/to DUT .