The Symbol Generator includes a software symbol generator (using Matlab) with a HW extractor (FPGA) using VHDL. Using a set of known symbols (such as letters, digits, icons, etc), all having in common the same dimensions, and are generated on the screen. The goal is to save time, resources and bandwidth. Therefore, the SW transfers to the HW only the change of the wanted frame from the current one, using a command for the HW, instead of sending the whole frame.
- Building a symbol generator block for FPGA in VHDL environment which:
- receive commands from Host.
- apply to external memory (SDRAM).
- 3. dispatch new display onto screen.
- Integrating the block into an existing platform FPGA.
