SAT Solver

After the conclusion of our previous project, in which we have developed a platform to implement SAT instances onto an FPGA device, along with a random SAT solver, we embarked on building a smarter platform that enables us to significantly cut down compilation times and more importantly to reduce the time it takes to find the satisfying assignment of a given SAT (run-times). the schemes we have implemented to meet our goals were:

• Building a sophisticated SAT solver GSAT
• Implementing an application specific SAT solver using the memory of the FPGA device.