Automatically generates registers according to a required specification using a smart interface.
In complicated FPGA designs, a common method to enable easy access to registers is by using one or more small register slave blocks for each functional block. The communication with these blocks will be by using a local bus protocol that connects all the register blocks in the entire design to the local bus master. Register slave blocks may have different features (such as the size of the register, the ability to read and/or write, etc.). AutoReg is an easy-to-use tool that gives designers the ability to automatically create VHDL code for register blocks, and will save time, create unity and prevent bugs. Key Features: 1. Comfortable easy to use experience. 2. Tree view for easy navigation inside the project. 3. Possibility to save or load projects. 4. Immidiate feedback on errors during the process.