This project presents a hardware-efficient implementation of a Multi Layer Perceptron (MLP) neural network on an Artix-7 FPGA, utilizing Y-Flash devices for neuromorphic computing. By integrating 4-bit quantization and in memory computing principles, the system demonstrates high performance digit recognition with optimized power and memory utilization.
Hardware Efficient Neural Network Implementation on FPGA using Y-Flash Neuromorphic Principles
This project explores the bridge between theoretical neuroscience and practical machine learning by implementing a hardware efficient MultiLayer Perceptron (MLP) on a Nexys A7 FPGA platform. The core objective is to bypass traditional computational bottlenecks specifically the energy-heavy data transfers between memory and processors by adopting In-Memory Computing (IMC) principles inspired by neuromorphic architectures.
The system utilizes Y-Flash devices as analog memory cells, where mathematical multiplication is replaced by physical properties. By leveraging Ohm’s Law, the hardware generates a current that represents the exact product of a pixel value (voltage) and a learned weight (conductance). To handle negative weights in an analog domain, a differential pair architecture is employed, representing signed values through the net current of two Y-Flash cells.
To fit within the constraints of edge FPGA hardware, specifically the 4,860 Kb limit of internal Block RAM (BRAM), the project implements a rigorous optimization pipeline. This includes a Max Pooling preprocessing layer that reduces the MNIST input from 784 to 196 features, and a 4-bit symmetric quantization strategy. This shift to integer arithmetic enables parallel Multiply-Accumulate (MAC) operations while ensuring hardware stability against analog variations.
The final implementation features a complete digital-analog pipeline, managed by an autonomous controller on the Artix-7 FPGA. The architecture consists of a three-layer network ,integrated with Pmod DA3 and AD5 converters to facilitate communication between the digital FPGA logic and the analog Y-Flash neurons. The result is a robust, real-time prediction system that demonstrates the potential of physical-based models in modern AI hardware design.
