Hardware description languages (HDLs) and high-level languages (HLLs) serve distinct roles in computer
development, with HDLs focusing on hardware specifics and high-level languages on software.
DFiant HDL aims to bridge this gap, offering a higher level of abstraction akin to high-level
languages while retaining the capabilities of HDLs. Taking an open source project named AD ASTRA, we translated
its design to DFiant's abstraction levels, showing that DFiant offers comparable performance with
shorter and more user-friendly code.
DFHDL is a new language designed to bridge the gap between HLLs and HDLs. It can be divided into three levels: Event-Driven(ED), Register Transfer(RT) and Dataflow(DF), with each level being based on the previous level.
Event-Driven Domain is similar and comparable to other HDLs like System Verilog(SV), changing signal’s values given inputs on specific time.
In Register Transfer level we configure a clock and reset domain in which each module will work. There are only non-blocking assignments in this level, and each variable needs to be defined as register or wire.
Dataflow Domain allows shorter and more direct coding using high level abstractions.
In our project we used an open-source project called “AD-ASTRA” as a baseline. The original project used the Arty-A7 board , therefore the first step was changing the project’s configurations to support the Xilinx zync-7000 zedboard.
After validating the baseline we then proceeded to translate the code in VSCode IDE from SV to ED Domain in DFHDL, module by module.
For each translated module we then examined the wave simulations to make sure its translation was accurate, which included writing testbenches for each one individually, and running the Verilator Simulator that manufactures the waves. We also used GDK tool of verilator to create the graphics of the design, allowing us to easily know if there are any mistakes or problems.
DFHDL is still being written, and so does not have support in the various known tools used to simulate designs.
In order to use those tools, we used SBT compiler to translate the code back to System Verilog, which we could then run in Verilator and Vivado.
After finishing the translation we ran synthesis and implementation using the Vivado tool and programmed the Zedboard with the project,
allowing us to see if the translation worked as expected.
Once the first step in translation was confirmed, we started on the second part – translating the design to RT level.
In order to assess our success, we used Vivado to compare different aspects of both the original code and the translated code we had written.
