Creating a 40Gbit Traffic Generator using an FPGA, a cheaper solution than using an IXIA
Debugging a modern communication chip requires the ability to generate high sped L1 & L2 Ethernet signals on all ports of the chip.
High speed Ethernet signals (10.3125 GHz) can be generated by commercial tools, e.g. IXIA, however they are expensive and deal mainly with higher software layers.
The proposed solution is to use an Altera ready made Ser-des board to generate the high speed signals based on programmable patterns.
The first step is to design the hardware and generate few hard coded patterns in 10GHz .
The second step will focus on enabling a control mechanism to the Signal Generator that would enable us to transmit different types of predefined packets in single shot mode and continuous mode, also, designing software to automate the insertion and creation of new predefined packets into the project’s RTL.