Our project of 40G signal tap is a design on an FPGA to service the requirement of modern day testing equipment. Our design allows tapping into a 40GBit traffic operating on the XLAUI protocol. The project is highly configurable allowing many PHY setups and high versatility. The work was done in an ALTERA Quartus environment on a StratixV board. During the project we have also successfully designed a PCB as a DDR- SOFT TOUCH interposer.
Modern day communication devices validation depends heavily on low level link and physical layer validation.
The next trend of network applications are the 40G/100G speeds, this advancement raises new challenges in device validation, while 10G applications have various test equipment and link partners, 40G/100G applications lack this validation framework. 40G traffic validation and generation equipment are still young in the industry, and may not always provide the versatility and the configuration freedom in such early stages of technology.
Providing a solution to this problem in such an early stage in an imperative part of development, designing a traffic validation device in the form of a link tap will help us verify the link’s properties and pinpoint link related problems.
The ability to tap on the line without having an effect on the existing link (unlike IXIA where it is the link partner and thus forcing IXIA related conditions) is imperative in validating new link features like EEE and alike.
Moreover, using link tap on the line, and defining our logic’s delay and latency we can measure latency related tests and measurements, which the industry lacks in providing.
Our joint Technion-Intel project, with collaboration with the 40G signal generation project, is the solution provided to address all those issues, and moreover, with relatively much lower cost.