Designing fast clock source with deterministic jitter for high speed phenomena experiment.
Designing and implementing a 4 times faster clock source unit . This unit will be used to build an engineering model to function as a 4 times faster clock source with deterministic jitter.
Designing and implementing “delays array bank”, which divides the clock source into four routes, which feed 4 consumers with clock signals. This clock signals arrive within predetermined skew intervals. This unit will be used for skew phenomena experiment.
Designing the printed circuit board which will be used to create 8 times faster clock source.
