Out of order Open Risc

Implementation of Out-of-Order execution engine on the base of OpenRISC architecture.

OpenRISC 1200 is open source CPU architecture. The goal of part A of the project is to build the System on a Chip based on OpenRISC architecture, implement it on XUPV5 board, and create the environment to ensure proper work and testability of the system. The goal of part B of the project is to biuld Out-of- Order micro-architecture based on OpenRISC and compare to inorder OpenRISC, using the platform that created during part A.