The ZED-board has an RGB output port. This port must be driven from logic in the reconfigurable logic portion of the FPGA. Aims is, to create a frame-buffer in memory, to be filled with data by a program running on an ARM, read its content via AIX DMA (Direct Memory Access) and send it to the logic to be created in VHDL for display on a RGB display.
Creating a system that enables reading images from an external device, saving it in the memory and displaying it by VGA.
Creating a programmable logic design that will handle the transportation of the data from the main memory to the VGA output via video direct mapped accessed (VDMA) component.