• In our project, we will design the implementation for the CEDAR algorithm over Hardware Description Language, and using functional simulations, we will demonstrate how the CEDAR algorithm can achieve low relative errors while keeping a small number of bits per counter.
    Tags: | | | | | |
  • The project compresses, using Run-length algorithm (sequences in which the same data value occurs in many consecutive data elements is stored as a single data value and count, rather than as the original run), image using MATLAB and transmits it, as a wrapped message, through UART protocol, to the DE2 board. The FPGA encodes the wrapped message, validate CRC and correct message length and stores the data into SDRAM. The...
    Tags: | | | |