• This project aim was to create an infrastructure who enable the end user to create and use hardware accelerators library using INtime for Windows RTOS and NetFPGA-SUME. Hardware accelerators are created with Xilinx Partial Reconfiguration technology that gives us the ability the ability to swap accelerators at real-time without affecting other operational part of the system.
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  • Building an infrastructure for hardware accelerators based on FPGAs for algorithms implemented in MATLAB. Consists of 3 main parts: - C code that is invoked from a MATLAB script (MEX file). - PCIe driver that is used to transfer data to the hardware. - Basic hardware design that connect the PCIe and the DDR3 memory DIMMs on the VC709 board.