• The subject of this project is to design and implement a combined software/hardware environment in which multiple algorithm computation units can be linked together across multiple FPGAs according to a certain multi-stage data flow. The multi-stage algorithm computation flow demonstrated by this project is the "Regularized Particle Filter using GPS/INS" algorithm . Particle filters are sequential Monte Carlo methods used to estimate various unknowns of a time-varying signal presented in...
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  • Nowadays, many VLSI (Very Large Scale Integration) components are manufactured in the industry. After manufacturing these components, there is need for component validation before composition in a larger system, or delivering the products to the client. In spring 2009, VLSI Lab offered a Tester for VLSI components project to HSDSL. In our project, the main idea was to create a custom HW and SW solution that will allow examining different...
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  • Developing a generic testnig system which supports up to 96 i/o pins, 100Mhz clock rate, loop mode (loop over the data according to loop commands received from the user ), adding embedded logic analyzer to view and anlyze the signals from/to DUT .
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  • The first block of the digital part of the Sub-Nyquist project. Takes 4 channels from the A2D which are sampled at high frequency (60[MHz]) and outputs 12 channels to the rest of the blocks at a lower sampling frequency (20[MHz]). The main purpose of this digital block is to use less analog hardware and to minimize costs.