• The subject of this project is to design and implement a combined software/hardware environment in which multiple algorithm computation units can be linked together across multiple FPGAs according to a certain multi-stage data flow. The multi-stage algorithm computation flow demonstrated by this project is the "Regularized Particle Filter using GPS/INS" algorithm . Particle filters are sequential Monte Carlo methods used to estimate various unknowns of a time-varying signal presented in...
    Tags: | |
  • Nowadays, many VLSI (Very Large Scale Integration) components are manufactured in the industry. After manufacturing these components, there is need for component validation before composition in a larger system, or delivering the products to the client. In spring 2009, VLSI Lab offered a Tester for VLSI components project to HSDSL. In our project, the main idea was to create a custom HW and SW solution that will allow examining different...
    Tags: | | | | | | |
  • "Real Time Tracking Algorithm On Low Cost Fpga" consists of two parts: Part A: A system that streams video to DE2 board and displays them on a CRT/LCD screen Part B: Implementation of a video tracking algorithm on FPGA both in hardware and software.
    Tags: | | | | |
  • The project is 2-semestrial and includes working with Altera DE-2 and DE-3 educational boards, USB analyzer and USB webcam. In the first part of the project we built and configured the system which runs on Altera DE2 board and operates USB interface with generic webcam. We implemented USB host interface which enables to detect, configure the video cam and get isochronous video stream. The video stream is then decoded and...
    Tags: | | | | | |
  • This project implements a high-speed digital communication channel switch. It is implemented on a Stratix II Gx SI development kit by Altera. It utilizes 4 ports and transfers 128-byte packets from port to port. It uses CRC error checking, and ALTGX physical channel.
  • In computer graphics, ray tracing is a technique for generating an image by tracing the path of light through pixels in an image plane and simulating the effects of its encounters with virtual objects. The technique is capable of producing a very high degree of visual realism, usually higher than typical scan-line rendering methods, but at a greater computational cost. This makes ray tracing best suited for applications where the...
  • In High - speed communication, data is usually transferred in a serial way, being de-serialized at the receiver. When no-handshake is used, synchronization and alignment problems may arise. The project goal is to solve this issue by adding a protocol layer over the physical layer, which allows data packets transfer between a transmitter and a receiver, while assuring it to be synchronized and aligned properly, with low error probability. The...
    Tags: |
  • In our project, we will design the implementation for the CEDAR algorithm over Hardware Description Language, and using functional simulations, we will demonstrate how the CEDAR algorithm can achieve low relative errors while keeping a small number of bits per counter.
    Tags: | | | | | |
  • Today, array sorting is a highly required task. Generating a photo histograms on cameras, folder and file trees on computers, displaying a contact list on a cell phone - all use sorting. Therefore, a quick and efficient sorter will be very useful. This project implements a sorting mechanism that receives an input stream of integer arrays and outputs sorting results in real time, and with zero latency. To do so,...
    Tags: | | | | | |
  • The Symbol Generator includes a software symbol generator (using Matlab) with a HW extractor (FPGA) using VHDL. Using a set of known symbols (such as letters, digits, icons, etc), all having in common the same dimensions, and are generated on the screen. The goal is to save time, resources and bandwidth. Therefore, the SW transfers to the HW only the change of the wanted frame from the current one, using...
    Tags: | | | |
  • The project implements an image processing algorithms with VHDL. The system burn on FPGA board, and supports: Full panoramic rotation: -360 to 360 degrees Zoom function- x1 to x16 Crop-Image function Minimum image distortion. Inputs - angle, zoom factor, crop coordinates, 512x512 BMP 8bit greyscale image. Output - processed 600x800 BMP 8bit greyscale image. Protocols - UART-software to hardware, WISHBONE-hardware to hardware. 
    Tags: | | | |
  • Implementation of mini digital scope. User can determine the pre and post trigger, trigger level, how many sequential times user want to find the trigger. Using the wishbone protocol for communication between different system blocks.
    Tags: | | | |
  • CORDIC is an acronym for COrdinate Rotation DIgital Computer.  It is a class of shift-add algorithms for rotating vectors in a plane.  In a nutshell, the CORDIC rotator performs a rotation using a series of specific incremental rotation angles selected so that each is performed by a shift and add operation.  The project goal is to implement the CORDIC algorithm in HDL language, choose optimal architecture and test it on FPGA card
    Tags: | | |
  • This project uses symbol generator infrastructure. The main goal is to enable navigation between symbols that can be generated in advance.
    Tags: | | |