The goal of this project is to design and implement an efficient architecture for reconstruction of a compressed image by DWT transform.
This project is a continuation of a project A, which implements frame compression and minimizing the original image by factor of 4, such that this project implements the compressed image reconstruction (increasing the image size in factor of 4). The architecture, implemented by hardware in VHDL, gets the compressed image in resolution of 256X256 and other related information as an input, and outputs the reconstructed image in a resolution of 512X512. The transform is 2D discrete transform such that, it operates on the rows-1 dimension, and later on the columns -1 dimension. The transform is discrete transform because, in computers, pixels are represented as discrete values. In addition, the project implements an interface to an appropriate simulation environment that demonstrates the correctness and efficiency of the algorithm at real time.