PCIe GEN 3.0 PBERT analyzer

Fast communication channels have become a necessary infrastructure in any digital system. Industry defines various standards for transmitting data, one of the most important and common ones is the PCIe.
The goal of the project is to design a Matlab GUI to allow the user to generate custom packets and Design a programmable data source for sending PCIe type package to a JBERT and analyze them there.

Fast communication channels have become a necessary infrastructure in any digital system. Industry defines various standards for transmitting data, one of the most important and common ones is the PCIe. It defines how and how fast the data is transmitted on the computer. One of the most commonly used tools for the development and testing of equipment that uses communication channels is an analyzer that can test the quality of communication and the efficiency with which data are transmitted.

 

The goal of the project was to Design a Matlab GUI to allow the user to generate custom packets, Implement different methods to generate data patterns and Design a programmable data source for sending PCIe type package to a PBERT and analyze them there.

 

In fact, we sent the information through the GUI we created in the Matlab. The data stream from the GUI will be received bit-by-bit into the FPGA through the USB interface. Once the UART messages arrived, they will be parsed into “W”, address and payload (two hex digits). The payload will be stored in the matching address in the register file which consists of 8 lines of 32 bits each (4 UART data’s). When the next line is fully registered, the controller will move it to the scramble block and allow it to be pushed to FIFO. When the FIFO contains all the lines, the controller will begin to pop the lines of it, and change the input to the transceiver from the default line to the popped line. The SERDES will receive the bits, serialize them into a 1 bit wide stream and send them out of the system to the PBERT in 8 Giga bit per second.