Apples Siri and Amazon’s Alexa are voice activated systems. Here a microphone is always active. It listens to the surrounding, samples and digitizes the data, analyses them to some extend and sends them to a host for final processing. The host may then activate or deactivate specific devices in a home.
This proposed project should enable the HSDSL ‘IoT experiment’ at a later stage to utilize voice activation. Therefore, a small microphone attaches to the Xilinx ZedBoard. The interface for the microphone is designed on the FPGA logic part of the ZYNQ-chip. The amplitude of the microphone output signal is monitored in hardware. After it reaches a defined noise-level, a defined number of samples (words) are loaded into the ARM part of the ZYNQ-chip. There it can be processed using normal C-code. Either the ARM itself can trigger an action on the ZedBoard or the preprocessed voice data stream is sent via Ethernet connection to a host.
Prerequisite: logic design
Duration: one semesters
Supervisor: Rolf Hilgendorf firstname.lastname@example.org