This project aim was to create an infrastructure who enable the end user to create and use hardware accelerators library using INtime for Windows RTOS and NetFPGA-SUME.
Hardware accelerators are created with Xilinx Partial Reconfiguration technology that gives us the ability the ability to swap accelerators at real-time without affecting other operational part of the system.
The purpose of this project is to open a communication channel between INtime (A Real Time OS) and Xilinx Partial Configuration technology in order to create an infrastructure for creating and using hardware accelerators dynamic library that we can be used on demand (AKA “hardware DLL’s”).
Thus achieving the final purpose of the project: software acceleration with hardware accelerators.
There are three main players in the project:
- INtime RTOS – an operating system that gives us deterministic, hard real-time control over processes with standard Windows operating systems
- NetFPGA-SUME- an advanced board that enable us fast commination between host computer and Xilinx FPGA (Via PCIe) thus does not settling performance.
- Xilinx Partial Reconfiguration -Partial reconfiguration is the process of changing a portion of reconfigurable hardware circuitry while the other part is still running/operating.
Combining those three factors we created a platform that enable us to create and run hardware accelerators.
This is the first part of the project the second part will focus on creating a much more robust framework, Implementing Task Oriented scheduler and compiler on INtime OS and Integrating Task Oriented Software and Hardware accelerators