Implementing RISK Processor using Bluespec

Implementing Pipelined MIPS processor using Bluespec System Verilog, and run it on FPGA.

Bluespec SystemVerilog (BSV) is a relatively new hardware description language (HDL), which characterizes in being a low-level HDL similar to System Verilog or VHDL, yet higher-level language.

In this project we explore the advantages of BSV in implementing a piplined MIPS processor in a higher-level HDL, whilst letting the bluespec compiler make the optimizations.