The goal of the project is to implement a sequencer - multi-channel digital pattern generator. The sequencer would be able to be clocked/triggered/reset and perform averaging and loops. The development would be using the VHDL and Virtex-7 evaluation board.
In this project sequencer system was built:
The rate of the sequencer is 100 MHz.
The sequencer loops on sequences that can contain loops (8 nested loops).
Each loop can have any number between 2 –1048000 of iterations.
The sequencer can loop on table that have 1-7000 instructions.