Developing mechanisms for testing high-speed communications channels

Fast communication channels have become an important basis of all fast digital system. From Smartphone and home PC to supercomputers. Following the demand for high speed data rate, the data transfer rate has increased over the years. The PCIE gen 1 had 3Gbit the PCIE4 will have 16Gbit. As a result, the problems in SI (Signal Integrity) had become critical. One of the most important SI problems is the jitter phenomenon.
Over the years, the jitter phenomenon was systematically analyzed. Standards have been established and sophisticated tools for testing and analysis had been developed. One of the most modern and advanced tool for jitter analysis on the market today is the JBERT N4903B from Agilent

scope2

Project goal

Analyzing various types of fast communication channels by using the JBERT tester. The Communication channels will be implemented by using FPGA chips which contains transmitters and receivers of fast communication channel (Ser/Des).

Different strategies of testing fast communication channels will be examine. We shell also test variety of mechanisms to improve the communication on the channel.

 

The Students will acquire knowledge in designing high-speed communications channels and the Jitter phenomenon.

 

Project prerequisite: digital systems

Supervisor: mony orbach email: mony@ee.technion.ac.il