In High - speed communication, data is usually transferred in a serial way, being de-serialized at the receiver. When no-handshake is used, synchronization and alignment problems may arise. The project goal is to solve this issue by adding a protocol layer over the physical layer, which allows data packets transfer between a transmitter and a receiver, while assuring it to be synchronized and aligned properly, with low error probability. The Data Stream Aligner is implemented on Altera Cyclone II FPGA (on DE2 Board). It is tested by a Matlab GUI which communicates with the FPGA via UART, and allows injecting stimulus packets to the unit under test and analyzing the results.
The high speed serial data transmitter sends serial data through SDATA line at rates of Giga-Hertz, according to SCLK (Serial clock) line. The ‘Serial to parallel’ block converts the serial data to parallel data (PDATA line) which corresponds to PCLK clock line (therefore, PCLK should be derived from SCLK, divided by the width of PDATA). Next, the alignment and synchronization blocks are responsible for determining when the received data is synchronized and aligned. The latter should also be able to produce useful information kept in the packets, such as the data length, type, address etc.