Hardware acceleration is necessary to improve network performance. The goal of the project is to implement compression of packets data in real time on a FPGA integrated inside a network card.
The exponential increase in data in the world present many challenges it terms of network traffic and congestion. To achieve better performance, become popular to offload part of the workload to hardware accelerators. Few examples of such hardware accelerations are; Data Encryption, Data Compression, Inspection of packets etc.
Mellanox Technologies provide a network card called “Innova Flex”. This card has on-board FPGA on it with area called “Sandbox”. The “Sandbox” allows the user to add its own logic, in order to influence the data passing through to card. By that, it is possible to implement algorithms in hardware that are offloading work from the CPU and accelerating the traffic.
The goal of the project was to implement a compression algorithm in the Innova Flex Sandbox. The compression based on detecting and eliminating sequences of zeros in the data payload of the packets, and adding a notation that indicates where such sequences were compressed, so it will be possible to decode the packet in the receiving side and construct the original packet back.
That design that implemented for the project was a pipelined design. That is, to preserve a principle called “Bump on the wire”. This means that the processing of the packets is done while the packet is “on the wires”, without altering the packet’s End-Points, and with minimal negative impact on the traffic latency and bandwidth.
