The aim of the project is to design the 5GSPS sample rate scope using a new and more cost effective technology of the DRS4 unit. A full electronic circuit scheme of the scope and a PCB design had been designed as a base for the future possible manufacture process.
For achieving the goal of the project, the unique qualities of the DRS4 chip were combined with other circuit components’ abilities. The modus operandi of DRS4 based on an array of switched capacitors, which are able to sample voltages of analog high-speed (1GHz) signals.
The design assumes different methods of sampling for the high-speed signals and for the low-speed ones, so the most cost-effective activity of the sampler will be achieved.
The low-speed signals does not need to the sampling abilities of the DRS4, so it will be in transparent mode. The high-speed signals, on the other hand, will be treated by the capacitors array.
- For high-speed signals the DRS4 will be triggered and use its ability to deal with high rates. A dedicated ADC will sample the saved data. The data will be downloaded from the mux output of the DRS4.
- For slow signals, the DRS4 will be in “transparent mode” (not triggered) and a different ADC will sample the data directly. The data will be downloaded from 4 output channels of the DRS4.
The waveform will display an integrated both fast and slow signals.