PCIe GEN 3.0 network analyzer

Fast communication channels have become a necessary infrastructure in any digital system. Industry defines various standards for transmitting data, one of the most important and common ones is the PCIe.
The goal of the project is to design designing and building a serial data receiver using the FPGA board, which receives data from the Jbert and forward it to transmitter which transmits it back to the JBERT and analyze the sent and received data there.

One of the most commonly used tools for the development and testing of equipment that uses communication channels is an analyzer that can test the quality of communication and the efficiency with which data are transmitted.

The goal of the project is to designing and building a serial data, which receives data from the Jbert and forward it to transmitter which transmits it back to the JBERT and analyze the sent and received data there, the communication will be in 8 Giga bit per second in PCIe standard.

The receiver will be implemented in VHDL code and will be run on FPGA board.

The project implemented two versions of the system, one with shifter for receiving fixed data, in this implementation it’s possible to debug and use the received data in addition to forwarding it to the transmitter to be transmitted back to the Jbert.

And second without shifter, for receiving random data (PRBS), this data will be forwarded directly to the transmitter to be transmitted back to the Jbert.