- Year - 2009
This project implements a generic system called RTMS, which is capable of running any real-time system, including: satellite system, robot and etc. In addition it simulates a satellite system which runs on RTMS, including a set of sensors and functions.
Nowadays, many VLSI (Very Large Scale Integration) components are manufactured in the industry. After manufacturing these components, there is need for component validation before composition in a larger system, or delivering the products to the client.
In spring 2009, VLSI Lab offered a Tester for VLSI components project to HSDSL. In our project, the main idea was to create a custom HW and SW solution that will allow examining different components. The tester project includes an ASIC* daughter board (HW) that is connected to an FPGA in the HSDS lab, and the different DUTs (device under test) will be connected to this board. The interaction with the components will be from an application (SW) to the FPGA, from the FPGA to the daughter board (written in VHDL) and from the DB to the DUTs through the board's pins that are connected to the components.
The project was divided to two parts and was given to two groups that together formed the project's entire group:
• Hardware group – in charge of developing the daughter board and creating the interaction with the FPGA (VHDL).
• Software group – in charge of developing the host application, which will enable the end user to test his component.
Eventually, these two parts are combined to one end-to-end project.
This document concludes the development of the SW part of the tester project.
Detecting a cellular device location in a given room by its signal, using a phased-array antenna. Our individual goal in this project was to check whether the system's behavior is close enough to theory - if not, then to do an adjustments and to solve other problems in the system, like reflections.
In High speed digital circuits, if Driver impedance is less than the tracer impedance of connected to Receiver, then overshoot and under shoot will occur and as a result signal will be ringing. Up to what level the signal overshoot and under shoot can be bearable. if over shoot signal will be with in the noise margin of the receiver level then what will be effect on the receiver signal due to overshoot.
The subject of this project is to design and implement a combined software/hardware environment in which multiple algorithm computation units can be linked together across multiple FPGAs according to a certain multi-stage data flow. The multi-stage algorithm computation flow demonstrated by this project is the "Regularized Particle Filter using GPS/INS" algorithm . Particle filters are sequential Monte Carlo methods used to estimate various unknowns of a time-varying signal presented in real time. The RPF algorithm combines GPS/INS inputs intended for navigation systems.